`srdatalog.ir.pipeline`¶

Pure compile pipeline — Program → compiled artifacts, no disk I/O.

build_project (build.py) and srdatalog.viz both want the same intermediate artifacts: HIR, MIR, per-rule runner code, schema defs, DB alias. The difference is what they do NEXT — build_project writes a .cpp tree to disk; viz renders in a webview.

Splitting the pipeline at the compile/write boundary lets both callers share the work. This module is that shared core.

Module Contents¶

Classes¶

CompileResult

Everything a downstream consumer (build_project, viz) needs from the compile pipeline, in memory.

Functions¶

compile_program

Run the full compile pipeline — HIR → MIR → all emitted strings.

API¶

class srdatalog.ir.pipeline.CompileResult[source]¶

Everything a downstream consumer (build_project, viz) needs from the compile pipeline, in memory.

canonical_indices: dict[str, list[int]]¶: ‘field(…)’

db_alias: str¶: None

device_db: str¶: None

ext_db: str¶: None

extra_headers: list[str]¶: ‘field(…)’

hir: srdatalog.ir.hir.types.HirProgram¶: None

mir: srdatalog.ir.mir.types.Program¶: None

per_rule_runners: list[tuple[str, str]]¶: None

rel_index_types: dict[str, str]¶: ‘field(…)’

runner_decls: dict[str, str]¶: None

schema_defs: str¶: None

step_bodies: list[str]¶: None

srdatalog.ir.pipeline.compile_program(program: srdatalog.dsl.Program, project_name: str) → srdatalog.ir.pipeline.CompileResult[source]¶

Run the full compile pipeline — HIR → MIR → all emitted strings.

Stops before any file I/O. The resulting CompileResult is the point both build_project (writes it to disk) and the viz module (renders it in a webview) branch from.